The present invention relates generally to the design and manufacture of integrated circuits, and more specifically, to decomposing a layout for triple patterning lithography.
An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Design engineers typically design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. IC design layouts typically include: (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC.
To create the design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts.
Fabrication foundries (“fabs”) manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., photomask) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries (i.e., features) of the IC design layout. The various geometries contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, via pads, as well as other elements that are not functional circuit elements, but that are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
Constraining factors in traditional photolithographic processes limit their effectiveness as circuit complexity continues to increase and transistor designs become more advanced and ever smaller in size (i.e., die shrink). Some such constraining factors are the lights/optics used within the photolithographic processing systems. Specifically, the lights/optics are band limited due to physical limitations (e.g., wavelength and aperture) of the photolithographic process. Therefore, the photolithographic process cannot print beyond a certain pitch, distance, and other such physical manufacturing constraints.
A pitch specifies a sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature. Depending on the photolithographic process at issue, factors such as optics and wavelengths of light or radiation restrict how small the pitch may be made before features can no longer be reliably printed to a wafer or mask. As such, the smallest size of any features that can be created on a wafer is severely limited by the pitch.
With the advance of ultra deep submicron technology, the feature size and feature pitch get so small that existing lithography processes meet their bottleneck in printing the shapes represented by the features. On the other hand, there are difficulties in the practical use of advanced photolithographic processes (e.g., extreme ultra violet (EUV)). Therefore, the current lithography technology is expected to be used for next generation silicon technology. To compensate for the difficulty in printing the shape of small pitches, multiple patterning lithography is recognized as a promising solution for 32 nm, 22 nm and sub-22 nm (e.g., 16 nm) volume IC production. Multiple patterning lithography technology generally decomposes a single layer of a layout into multiple masks and applies multiple exposures to print the shapes in the layer. The decomposition provided by multiple patterning lithography increases shape printing pitch and improves the depth of focus.
Double patterning lithography is one type of multiple patterning lithography technology that has been in use for some time. Double patterning lithography generally involves placing shapes that are too close to each other to be assigned to the same mask layer, onto two different mask layers in order to satisfy spacing requirements specified in the design layout. These two different mask layers are then used to print one design layer. However, for a dense layer of a layout (e.g. a first metal level (M1)), the double patterning lithography is not enough to print the shapes of the layer while maintaining the M1 pitch spacing requirements. This gives rise to explore other multiple patterning lithography options such as triple patterning lithography.